(Not Applicable)
(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package having a rail configuration which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages which each include a rail configuration. The inclusion of rail members in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significantly greater simplicity in such assembly.
In accordance with a first embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising an interconnect sub-assembly. The interconnect sub-assembly itself comprises an interconnect substrate which defines opposed, generally planar top and bottom surfaces. The interconnect substrate preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The interconnect substrate is preferably flexible, though the same may alternatively be of rigid construction. If flexible, the interconnect substrate is preferably fabricated from a polyamide. If of rigid construction, the interconnect substrate is preferably fabricated from a ceramic material.
Disposed on the interconnect substrate are first, second and third conductive pad arrays, with the second and third pad arrays extending along respective ones of the lateral peripheral edge segments of the interconnect substrate and being disposed on opposite sides of the first conductive pad array. Additionally, the second and third conductive pad arrays are each electrically connected to the first conductive pad array. The electrical connection of the second and third conductive pad arrays to the first conductive pad array is preferably facilitated by conductive tracings which are formed in accordance with conventional etching techniques.
In the chip package of the first embodiment, the first conductive pad array comprises a first set of pads disposed on the top surface of the interconnect substrate, with the second conductive pad array comprising second and third sets of pads disposed on respective ones of the top and bottom surfaces and arranged in identical patterns such that the pads of the second set are aligned with respective ones of the pads of the third set. Similar to the second conductive pad array, the third conductive pad array comprises fourth and fifth sets of pads disposed on respective ones of the top and bottom surfaces and arranged in identical patterns such that the pads of the fourth set are aligned with respective ones of the pads of the fifth set. The pads of the second set are electrically connected to respective ones of the pads of the third set, with the pads of the fourth set being electrically connected to respective ones of the pads of the fifth set. Such electrical connection may be facilitated through the use of vias extending through the interconnect substrate or conductive tracings which extend about the lateral peripheral edge segments thereof.
The interconnect sub-assembly of the chip package of the first embodiment further comprises first and second identically configured rail members which are each attached to the interconnect substrate. The first and second rail members each have a generally rectangular configuration and define opposed, generally planar top and bottom surfaces. Disposed on the first rail member is a fourth conductive pad array, while disposed on the second rail member is a fifth conductive pad array. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays.
The fourth conductive pad array itself preferably comprises sixth and seventh sets of pads which are disposed on respective ones of the top and bottom surfaces of the first rail member and arranged in identical patterns such that the pads of the sixth set are aligned with respective ones of the pads of the seventh set. Similarly, the fifth conductive pad array preferably comprises eighth and ninth sets of pads which are disposed on respective ones of the top and bottom surfaces of the second rail member and arranged in identical patterns such that the pads of the eighth set are aligned with respective ones of the pads of the ninth set. The pads of the sixth set are electrically connected to respective ones of the pads of the seventh set, with the pads of the eighth set being electrically connected to respective ones of the pads of the ninth set. In the chip package of the first embodiment, the pads of the second through fifth sets (which are disposed upon the interconnect substrate), the pads of the sixth and seventh sets (which are disposed upon the first rail member) and the pads of the eighth and ninth sets (which are disposed upon the second rail member) are arranged in identical patterns.
The interconnect sub-assembly of the chip package of the first embodiment is preferably assembled by attaching the first and second rail members to the interconnect substrate such that either the sixth or seventh sets of pads of the first rail member are electrically connected to respective ones of those pads of the second conductive pad array which are disposed on the bottom surface of the interconnect substrate, and either the eight or ninth sets of pads of the second rail member are electrically connected to respective ones of those pads of the third conductive pad array which are disposed on the bottom surface of the interconnect substrate. The electrical connections between the first and second rail members and the interconnect substrate in the interconnect subassembly, and more particularly between the fourth and fifth conductive pad arrays and respective ones of the second and third conductive pad arrays, may be facilitated through either the use of solder or an adhesive such as a conductive epoxy or a z-axis adhesive.
In addition to the interconnect sub-assembly, the chip package of the first embodiment comprises an integrated circuit chip which is electrically connected to the first conductive pad array, and hence to the second and third conductive pad arrays by virtue of their electrical connection to the first conductive pad array. The integrated circuit chip preferably comprises a flip chip device or a fine pitch BGA (ball grid array) device having a body which is of a generally rectangular configuration defining opposed, generally planar top and bottom surfaces, a pair of longitudinal sides, and a pair of lateral sides. Protruding from the bottom surface of the body are a plurality of generally semi-spherically shaped conductive contacts which are preferably arranged in an identical pattern to the first set of pads. The electrical connection of the integrated circuit chip to the first conductive pad array is preferably facilitated by soldering the conductive contacts of the integrated circuit chip to respective ones of the pads of the first set. The integrated circuit chip is preferably sized relative to the interconnect substrate of the interconnect sub-assembly such that when the conductive contacts are electrically connected (e.g., soldered) to respective ones of the pads of the first set, the longitudinal sides of the body are substantially flush with respective ones of the longitudinal peripheral edge segments of the interconnect substrate, with the lateral sides of the body being disposed in spaced relation to respective ones of the lateral peripheral edge segments of the interconnect substrate so as not to cover any portion of the second-and third conductive pad arrays extending therealong.
In assembling the chip package of the first embodiment, the conductive contacts of the integrated circuit chip are electrically connected to respective ones of the pads of the first set comprising the first conductive pad array of the interconnect substrate of the interconnect sub-assembly. Such electrical connection is also preferably facilitated through either a soldering or adhesive bonding process.
In accordance with a modified version of the first embodiment, the interconnect substrate may include a pair of heat dissipating fin portions protruding laterally from respective ones of the longitudinal peripheral edge segments thereof. In this modified version, the interconnect substrate preferably comprises top, middle and bottom layers disposed in laminar juxtaposition to each other, with the top and bottom layers being fabricated from a polymer material and the middle layer being fabricated from a metallic material and defining the fin portions. When the fin portions are included on the interconnect substrate, the chip package may further comprise a pair of heat dissipation members which are attached to respective ones of the fin portions.
Further in accordance with the present invention, there is provided a chip stack comprising at least two of the above-described stackable integrated circuit chip packages. In the present chip stack, the chip packages are assembled such that the fourth and fifth conductive pad arrays of the first and second rail members of the interconnect sub-assembly of one of the chip packages within the chip stack are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate of the interconnect sub-assembly of another chip package within the chip stack. More particularly, those pads of the fourth and fifth conductive pad arrays of one of the chip packages in the stack which are not electrically connected to the interconnect substrate thereof are electrically connected to respective ones of those pads of the second and third conductive pad arrays of another chip package within the chip stack which are disposed on the top surface of the interconnect substrate of the interconnect sub-assembly thereof.
In addition to one or more chip packages, the chip stack of the present invention comprises a base package which includes a generally rectangular interconnect substrate defining opposed, generally planar top and bottom surfaces, a pair of longitudinal peripheral edge segments, and a pair of lateral peripheral edge segments. Disposed on the top surface of the interconnect substrate of the base package is a sixth conductive pad array, while disposed on the bottom surface thereof is a seventh conductive pad array which is identically configured to the sixth conductive pad array and electrically connected thereto. In addition to being identically configured to each other, the sixth and seventh conductive pad arrays are identically configured to the first conductive pad array of the chip package(s) within the chip stack. Also disposed on the top surface of the interconnect substrate of the base package are eighth and ninth conductive pad arrays which extend along respective ones of the lateral peripheral edge segments and are disposed on opposite sides of the sixth conductive pad array. The eighth and ninth conductive pad arrays are each electrically connected to the sixth conductive pad array, with such electrical connection preferably being facilitated via conductive tracings which are formed in accordance with conventional etching techniques. The eighth and ninth conductive pad arrays of the base package are identically configured to the second, third, fourth and fifth conductive pad arrays of the chip package(s) in the chip stack.
In the interconnect substrate of the base package, the sixth conductive pad array comprises a tenth set of pads, with the seventh conductive pad array comprising an eleventh set of pads which are arranged in an identical pattern to the tenth set of pads such that the pads of the tenth set are aligned with respective ones of the pads of the eleventh set. The pads of the tenth set are electrically connected to respective ones of the pads of the eleventh set through the use of, for example, vias which extend through the interconnect substrate of the base package.
In addition to the interconnect substrate, the base package of the chip stack comprises an integrated circuit chip which electrically connected to the sixth conductive pad array. The integrated circuit chip of the base package is configured identically to the integrated circuit chip of the chip package(s) in the chip stack, with the electrical connection to the interconnect substrate preferably being facilitated by soldering the conductive contacts of the integrated circuit chip to respective ones of the pads of the tenth set. The interconnect substrate of the base package may also be of either a flexible or rigid construction.
In assembling the chip stack of the present invention, the fourth and fifth conductive pad arrays of the first and second rail members of the interconnect sub-assembly of the lowermost chip package in the chip stack are electrically connected to respective ones of the eighth and ninth conductive pad arrays of the base package. More particularly, those pads of the fourth and fifth conductive pad arrays of the lowermost chip package which are not electrically connected to the interconnect substrate of the interconnect sub-assembly thereof are electrically connected to respective ones of the pads of the eighth and ninth conductive pad arrays of the base package which are disposed on the top surface of the interconnect substrate thereof. In a preferred embodiment, the chip stack includes more than two chip packages which are stacked upon a base package.
In accordance with a second embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising an interconnect sub-assembly. The interconnect sub-assembly itself comprises on interconnect substrate which has a generally rectangular configuration and defines opposed, generally planar top and bottom surfaces, a pair of longitudinal peripheral edge segments, and a pair of lateral peripheral edge segments. Similar to the interconnect substrate of the chip package of the first embodiment, the interconnect substrate of the interconnect sub-assembly of the chip package of the second embodiment may be of either flexible or rigid construction. If flexible, the interconnect substrate is preferably fabricated from a polyamide. If of rigid construction, the interconnect substrate is preferably fabricated from a ceramic material.
Disposed on the interconnect substrate are first and second conductive pad arrays, with the second conductive pad array extending along the longitudinal and lateral peripheral edge segments. The second conductive pad array is electrically connected to the first conductive pad array, with such electrical connection preferably being facilitated by conductive tracings which are formed in accordance with conventional etching techniques. The first conductive pad array preferably comprises a first set of pads disposed on the top surface of the interconnect substrate, with the second conductive pad array preferably comprising second and third sets of pads disposed on respective ones of the top and bottom surfaces and arranged in identical patterns such that the pads of the second set are aligned with respective ones of the pads of the third set. The pads of the second set are electrically connected to respective ones of the pads of the third set either through the use of vias extending through the interconnect substrate or conductive tracings which extend about the longitudinal and lateral peripheral edge segments thereof.
The interconnect sub-assembly of the chip package of the second embodiment further comprises first and second identically configured rail member which are each attached to the interconnect substrate. The first rail member has a third conductive pad array disposed thereon, with the second rail member having a fourth conductive pad array disposed thereon. The third and fourth conductive pad arrays of the first and second rail members are each electrically connected to the second conductive pad array, and hence the first conductive pad array.
In addition to the interconnect sub-assembly, the chip package of the second embodiment includes an integrated circuit chip which is electrically connected to the first conductive pad array. The integrated circuit chip is identically configured to that previously described in relation to the first embodiment, with the semi-spherically shaped conductive contacts thereof being arranged on the bottom surface of the body in an identical pattern to the first set of pads comprising the first conductive pad array. In this respect, the electrical connection of the integrated circuit chip to the first conductive pad array is preferably facilitated by soldering or adhesively securing the conductive contacts to respective ones of the pads of the first set. In the second embodiment, the integrated circuit chip is sized relative to the interconnect substrate such that the longitudinal sides of the body of the integrated circuit chip are disposed in spaced relation to respective ones of the longitudinal peripheral edge segments of the interconnect substrate of the interconnect sub-assembly. Additionally, the lateral sides of the body of the integrated circuit chip are disposed in spaced relation to respective ones of the lateral peripheral edge segments of the interconnect substrate such that the body does not cover any portion of the second conductive pad array which extends about the body of the integrated circuit chip.
Still further in accordance with the present invention, there is provided a method of assembling a stackable integrated circuit chip package. The method comprises the initial step of electrically connecting an integrated circuit chip to a conductive pattern on an interconnect substrate through the use of a soldering process/technique or alternatively through the use of an adhesive such as a conductive epoxy or a z-axis adhesive. Thereafter, first and second rail members are electrically connected to the conductive pattern such that the first and second rail members are electrically connectable to at least one other stackable integrated circuit chip package. More particularly, the first and second rail members each include a conductive pattern thereon, with the conductive patterns of the first and second rail members being soldered to the conductive pattern of the interconnect substrate.
Still further in accordance with the present invention, there is provided a method of assembling a chip stack. The method comprises the initial step of providing a plurality of panels which each have opposed, generally planar surfaces, a plurality of openings disposed therein, and a plurality of conductive pads disposed on the opposed surfaces thereof. Also provided in the present method are a plurality of substrate sheets which each have opposed, generally planar surfaces and a plurality of conductive pads disposed on at least one of the opposed surfaces thereof, and a plurality of integrated circuit chips which each have opposed, generally planar sides and include conductive contacts protruding from one of the opposed sides thereof.
In the chip stack assembly method, one of the panels is stacked upon one of the substrate sheets such that at least some of the conductive pads of the panel are disposed on at least some of the conductive pads of the substrate sheet. Thereafter, integrated circuit chips are placed into respective ones of the openings of the panel such that the conductive contacts of each of the integrated circuit chips are disposed on at least some of the conductive pads of the substrate sheet. Another substrate sheet is then stacked upon the panel such that the substrate sheet covers the openings of the panel and the integrated circuit chips therewithin, and at least some of the conductive pads of the substrate sheet are disposed on at least some of the conductive pads of the panel. Integrated circuit chips are then placed upon the substrate sheet such that at least some of the conductive contacts of the integrated circuit chips are disposed on at least some of the conductive pads of the substrate sheet. The stacking and placement steps may be repeated depending on the desired size/height of the chip stack. Finally, the conductive contacts of the integrated-circuit chips are bonded to at least some of the conductive pads of the substrate sheet upon which the integrated circuit chips are positioned, with at least some of the conductive pads of each of the substrate sheets being bonded to at least some of the conductive pads of at least one of the panels. Such bonding is preferably facilitated through the use of solder or an adhesive such as a conductive epoxy or a z-axis adhesive which is pre-applied to the conductive contacts and/or conductive pads and facilitates the bonding/electrical connections therebetween when the assembled chip stack is exposed to a high level of heat (e.g., placed into an oven).
Still further in accordance with the present invention, there is provided another method of assembling a chip stack. The method comprises the initial step of providing a plurality of panel assemblies, each of which includes a panel having opposed, generally planar surfaces, a plurality of openings disposed therein, and a plurality of conductive pads disposed on the opposed surfaces thereof. Also included in each panel assembly is a substrate sheet which has opposed, generally planar surfaces and a plurality of conductive pads disposed on at least one of the opposed surfaces thereof. The panel and substrate sheet are attached to each other such that at least some of the conductive pads of the panel are electrically connected to at least some of the conductive pads of the substrate sheet. Also provided in this alternative method are a plurality of shim sheets which each have opposed, generally planar surfaces, and a plurality of intergrated circuit chips which each have opposed, generally planar sides and include conductive contacts protruding from one of the opposed sides thereof.
In the alternative chip stack assembly method, the intergrated circuit chips may be placed into respective ones of the openings of the panel of one of the panel assemblies. Thereafter, a shim sheet is stacked upon the panel assembly such that the shim sheet is in abutting contact with the panel of the panel assembly and the integrated circuit chips and conductive pads of the panel assembly are aligned with respective ones of the openings of the shim sheet and are not covered thereby. Another panel assembly is then stacked upon the shim sheet such that the substrate sheet of the subsequently stacked panel assembly is in direct contact with the shim sheet and at least some of the conductive pads of such substrate sheet are in aligned contact with the conductive contacts of the integrated circuit chips. Integrated circuit chips are then placed upon the substrate sheet in the stack which is not in abutting contact with any shim sheet. The stacking and placement steps may be repeated depending on the desired size/height of the chip stack. Finally, the conductive contacts of the integrated circuit chips are bonded to at least some of the conductive pads of the substrate sheet upon which the integrated circuit chips are positioned, with at least some of the conductive pads of the panel assemblies being bonded to each other. Such bonding may be facilitated through the use of solder or an adhesive such as a conductive epoxy or z-axis adhesive which is pre-applied to the conductive contacts and/or conductive pads and facilitates the bonding/electrical connections therebetween when the assembled chip stack is exposed to a high level of heat.